1) Field of the Invention
The present invention relates to a technology for connecting a plurality of semiconductor chips to each other and sealing the chips in one package.
2) Description of the Related Art
In a System-in-Package type semiconductor device (hereinafter referred to as SiP type semiconductor device), a logic chip and at least one memory chip (for example, DRAM chip, SRAM chip, or flash memory chip) are connected to each other, as a plurality of semiconductor chips, and sealed in one package. The logic chip is connected to an external connection terminal, and the memory chip is connected to the external connection terminal via the logic chip. One of examples of the configuration is disclosed in Japanese Patent Application Laid-Open No. 10-283777.
In order to conduct a test on semiconductor devices in a packaged state or screening initial defects of the devices, it is necessary to conduct an accelerated life test when products are shipped. However, in the SiP type semiconductor device, input/output of the memory chip to/from outside cannot be directly performed, and must be performed via the logic chip at any time. Hence, there is a problem in that a test on the logic chip can be singly conducted, but a test on the memory chip cannot be singly conducted.